Huawei unveils new chip design approach

Huawei has introduced its new chip design approach at a major industry conference in Shanghai, termed the Tau Scale Law – a guiding principle for the future of semiconductors.

The announcement marks a potential new path for sustainable evolution as the traditional roadmap of Moore’s Law, which held that transistor density would double every 18 to 24 months, has slowed due to physical and economic constraints.

During the keynote speech at the ongoing IEEE 2026 International Symposium on Circuits and Systems, Huawei’s Semiconductor Business Department President He Tingbo explained that this new approach allows the industry to focus on reducing signal delay rather than continuously shrinking transistor size, known as geometric scaling.

“Named after the Greek letter tau (τ), which represents the time constant in physics, this approach aims to systematically reduce signal delays across electronic systems,” he said.

The core idea is that task completion time, not individual transistor size, should be the target for optimising electronic systems. Chips can become faster, more energy-efficient, and more densely integrated without solely relying on shrinking individual transistors.

In line with this, Huawei has employed a technique called LogicFolding, which rearranges circuit layouts to shorten the physical paths electrical signals must travel, He explained. This reduces resistance and capacitance, effectively boosting transistor performance and density.

According to He, Huawei has applied this principle across various levels, from individual devices to entire computing systems. Over the past six years, the company has designed and mass-produced 381 different chips using the Tau Scale Law, serving multiple industries.

“Huawei plans to launch a new Kirin chip this autumn, which will be the first to fully integrate LogicFolding architecture for significant performance improvements,” He said.

Looking ahead, Huawei projects that advanced chips designed under the Tau Scale Law will achieve transistor density equivalent to a 1.4-nanometre process by 2031.

“We believe openness and collaboration are key to driving sustainable progress in the semiconductor industry,” he added. He also called on global scientists, engineers, and industry partners to collaborate under the Tau Scale Law to ensure the sustainable evolution of semiconductors and electronics.